hexfet ? power mosfet fifth generation hexfet ? power mosfets from international rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the d 2 pak is a surface mount power package capable of accommodating die sizes up to hex-4. it provides the highest power capability and the lowest possible on- resistance in any existing surface mount package. the d 2 pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0w in a typical surface mount application. the through-hole version (IRL1004L) is available for low- profile application. s d g v dss = 40v r ds(on) = 0.0065 w i d = 130a ? l advanced process technology l ultra low on-resistance l dynamic dv/dt rating l 175c operating temperature l fast switching l fully avalanche rated description 12/29/99 www.irf.com 1 irl1004s IRL1004L d 2 pak irl1004s to-262 IRL1004L parameter typ. max. units r q jc junction-to-case CCC 0.75 r q ja junction-to-ambient ( pcb mounted,steady-state)* CCC 40 thermal resistance c/w parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v ? 130 ? i d @ t c = 100c continuous drain current, v gs @ 10v ? 92 ? a i dm pulsed drain current ?? 520 p d @t a = 25c power dissipation 3.8 w p d @t c = 25c power dissipation 200 w linear derating factor 1.3 w/c v gs gate-to-source voltage 16 v e as single pulse avalanche energy ? 700 mj i ar avalanche current ? 78 a e ar repetitive avalanche energy ? 20 mj dv/dt peak diode recovery dv/dt ?? 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case) c absolute maximum ratings l logic-level gate drive pd - 91644a
irl1004s/1004l 2 www.irf.com ? repetitive rating; pulse width limited by max. junction temperature. (see fig. 11) ? i sd 78a, di/dt 370a/s, v dd v (br)dss , t j 175c notes: ? starting t j = 25c, l = 0.23mh r g = 25 w , i as = 78a. (see figure 12) ? pulse width 300s; duty cycle 2%. s d g parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) ? CCC CCC showing the i sm pulsed source current integral reverse (body diode) ?? CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 78a, v gs = 0v ? t rr reverse recovery time CCC 78 120 ns t j = 25c, i f = 78a q rr reverse recoverycharge CCC 180 270 nc di/dt = 100a/s ?? t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) 130 ? 520 a ? calculated continuous current based on maximum allowable junction temperature; for recommended current-handing of the package refer to design tip # 93-4 * when mounted on 1" square pcb ( fr-4 or g-10 material ). for recommended footprint and soldering techniques refer to application note #an-994. ? uses irl1004 data and test conditions source-drain ratings and characteristics parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 40 CCC CCC v v gs = 0v, i d = 250a d v (br)dss / d t j breakdown voltage temp. coefficient CCC 0.04 CCC v/c reference to 25c, i d = 1ma CCC CCC 0.0065 v gs = 10v, i d = 78a ? CCC CCC 0.009 w v gs = 4.5v, i d = 65a ? v gs(th) gate threshold voltage 1.0 CCC v v ds = v gs , i d = 250a g fs forward transconductance 63 CCC CCC s v ds = 25v, i d = 78a ? CCC CCC 25 a v ds = 40v, v gs = 0v CCC CCC 250 v ds = 32v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 v gs = 16v gate-to-source reverse leakage CCC CCC -100 na v gs = -16v q g total gate charge CCC CCC 100 i d = 78a q gs gate-to-source charge CCC CCC 32 nc v ds = 32v q gd gate-to-drain ("miller") charge CCC CCC 43 v gs = 4.5v, see fig. 6 and 13 ?? t d(on) turn-on delay time CCC 16 CCC v dd = 20v, t r rise time CCC 210 CCC i d = 78a, t d(off) turn-off delay time CCC 25 CCC ns r g = 2.5 w, t f fall time CCC 14 CCC r d = 0.18 w , see fig. 10 ?? between lead, CCC CCC and center of die contact c iss input capacitance CCC 5330 CCC v gs = 0v c oss output capacitance CCC 1480 CCC pf v ds = 25v c rss reverse transfer capacitance CCC 320 CCC ? = 1.0mhz, see fig. 5 ?? electrical characteristics @ t j = 25c (unless otherwise specified) r ds(on) static drain-to-source on-resistance i gss i dss drain-to-source leakage current l s internal source inductance 7.5 nh
irl1004s/1004l www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 100 1000 10000 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 7.0v 5.5v 4.5v 4.0v 3.5v 2.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 2.7v 1 10 100 1000 0.1 1 10 100 20 s pulse width t = 175 c j top bottom vgs 15v 10v 7.0v 5.5v 4.5v 4.0v 3.5v 2.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 2.7v 0.1 1 10 100 1000 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 v = 50v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j t = 175 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 2.5 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 130a
irl1004s/1004l 4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 0 2000 4000 6000 8000 10000 v , drain-to-source voltage (v) c, capacitance (pf) ds v c c c = = = = 0v, c c c f = 1mhz + c + c c shorted gs iss g s g d , ds rss g d oss ds g d c iss c oss c rss 0 30 60 90 120 150 180 0 2 4 6 8 10 12 q , total gate charge (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 78 a v = 20v ds v = 32v ds 0.1 1 10 100 1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 175 c j 1 10 100 1000 10000 1 10 100 operation in this area limited by r ds(on) sin g le pulse t t = 175 c = 25 c j c v , drain-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms
irl1004s/1004l www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10v + - v dd 25 50 75 100 125 150 175 0 20 40 60 80 100 120 140 t , case temperature ( c) i , drain current (a) c d limited by package 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
irl1004s/1004l 6 www.irf.com d.u.t. v ds i d i g 3ma v gs .3 m f 50k w .2 m f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13b. gate charge test circuit fig 12c. maximum avalanche energy vs. drain current 25 50 75 100 125 150 175 0 300 600 900 1200 1500 1800 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 32a 55a 78a fig 12a. unclamped inductive test circuit fig 12b. unclamped inductive waveforms v ds l d.u.t. v dd i as t p 0.01 w r g + - t p v ds i as v dd v (br)dss 4.5 v q g q gs q gd v g charge fig 13a. basic gate charge waveform 4.5 v
irl1004s/1004l www.irf.com 7 p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfet ? power mosfets * v gs = 5v for logic level devices peak diode recovery dv/dt test circuit ? ? ? r g v dd dv/dt controlled by r g driver same type as d.u.t. i sd controlled by duty factor "d" d.u.t. - device under test d.u.t circuit layout considerations low stray inductance ground plane low leakage inductance current transformer ? *
irl1004s/1004l 8 www.irf.com d 2 pak package outline d 2 pak part marking information 10.16 (.400) r e f. 6.47 (.255) 6.18 (.243) 2.61 (.103) 2.32 (.091) 8.89 (.350) r e f. - b - 1.32 (.052) 1.22 (.048) 2.79 (.110) 2.29 (.090) 1.39 (.055) 1.14 (.045) 5.28 (.208) 4.78 (.188) 4.69 (.185) 4.20 (.165) 10.54 (.415) 10.29 (.405) - a - 2 1 3 15.49 (.610) 14.73 (.580) 3x 0.93 (.037) 0.69 (.027) 5.08 (.200) 3x 1.40 (.055) 1.14 (.045) 1.78 (.070) 1.27 (.050) 1.40 (.055) m ax. notes: 1 dimensions after solder dip. 2 dimensioning & tolerancing per ansi y14.5m, 1982. 3 controlling dimension : inch. 4 heatsink & lead dimensions do not include burrs. 0.55 (.022) 0.46 (.018) 0.25 (.010) m b a m minimum recommended footprint 11.43 (.450) 8.89 (.350) 17.78 (.700) 3.81 (.150) 2.08 (.082) 2x lead assignments 1 - gate 2 - d ra in 3 - source 2.54 (.100) 2x part number international rectifier logo date code (yyw w ) yy = year ww = week assembly lot code f530s 9b 1m 9246 a
irl1004s/1004l www.irf.com 9 to-262 part marking information to-262 package outline
irl1004s/1004l 10 www.irf.com world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252 7105 ir great britain: hurst green, oxted, surrey rh8 9bb, uk tel: ++ 44 1883 732020 ir canada: 15 lincoln court, brampton, ontario l6t3z2, tel: (905) 453 2200 ir germany: saalburgstrasse 157, 61350 bad homburg tel: ++ 49 6172 96590 ir italy: via liguria 49, 10071 borgaro, torino tel: ++ 39 11 451 0111 ir japan: k&h bldg., 2f, 30-4 nishi-ikebukuro 3-chome, toshima-ku, tokyo japan 171 tel: 81 3 3983 0086 ir southeast asia: 1 kim seng promenade, great world city west tower, 13-11, singapore 237994 tel: ++ 65 838 4630 ir taiwan: 16 fl. suite d. 207, sec. 2, tun haw south road, taipei, 10673, taiwan tel: 886-2-2377-9936 data and specifications subject to change without notice. 12/99 d 2 pak tape & reel information 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 ( .42 9 ) 10.70 ( .42 1 ) 16.10 ( .63 4 ) 15.90 ( .62 6 ) 1.75 ( .06 9 ) 1.25 ( .04 9 ) 11.60 ( .457 ) 11.40 ( .449 ) 15.42 ( .609 ) 15.22 ( .601 ) 4.72 ( .136 ) 4.52 ( .178 ) 24.30 ( .9 57 ) 23.90 ( .9 41 ) 0.368 ( .0145 ) 0.342 ( .0135 ) 1.60 ( .06 3 ) 1.50 ( .05 9 ) 13.50 (.532) 12.80 (.504) 330.00 (14.173) m a x. 27.40 (1.079) 23.90 (.941) 60.00 ( 2.362 ) m in . 30.40 (1.197) m ax . 26.40 ( 1.039 ) 24.40 ( .961 ) notes : 1. comforms to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge.
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